120
Network-on-Chip
Stripe
memory
49
27
363
357
362
IDCT
Quantizer
AC/DC
prediction
Inverse
scan
353
300
UP
sampler
VOP
recorder
500
313
362
70
157
16
16
16
16
16
16
313
94
Padding
VOP
memory
UP
sampler
Memory
Reference
memory
Arithmetic
decoder
Variable length
decoder
Run-length
decoder
DMUX
Down sampler
and context
calculator
Figure 5.1
Block diagram of a VOPD, IDCT, Inverse Discrete Cosine Transform; DMUX, Demultiplexer.
into the various strategies adopted to solve the problem. To start with, we
will look into the mathematical definition of the problem.
5.2 Mapping Problem
Given an application consisting of a set of communicating tasks, the first step
toward NoC realization is to identify the cores to carry out the tasks. After
the cores participating in an application have been decided, the application
can be represented in the form of a core graph, which is defined as follows:
Definition 5.1
The core graph for an application is a directed graph, G(C, E) with each vertex
c i ∈ C representing a core and the directed edge e i,j ∈ E representing the communication between the cores c i andc j . The weight of the edge e i,j , denoted by comm i,j ,
represents the bandwidth requirement of the communication from c i to c j .
However, the given NoC topology can be represented in the form of a
topology graph.