84
Network-on-Chip
In the simulation process, the parameters ρ and HP have been set to 0.3 and
0.75, respectively. Hence, from Equations 4.5 and 4.6, the values of α ON and
α OFF are calculated to be 1.5 and 1.21, respectively. The packet injection rate
within the ON slot is varying as 0.002, 0.004, 0.006, and so on. The user may
also choose between uniform and localized traffic patterns. In our simulation, we have fixed the packet length to be of 64 flits, as in the work of Pande
et al. (2005). The packet injection is continued for a simulation time of 200,000
cycles of the routers’ clock including 10,000 cycles to make the network stable from initial transient effects. For accurate estimation of the energy consumption, we have assumed that each traffic generator module injects traffic
into the network with a switching activity of 0.9 as it is expected to introduce
a large number of transitions, and thus energy consumption in the network.
4.3 Selection of Channel Width and Flit Size
To design a NoC-based system, selection of flit size and channel width plays
a crucial role in the overall system performance and cost. Although there are
several works reported in the literature that use wider flits [e.g., 64 bits (Soteriou
et al. 2007), 96 bits (Rijpkema et al. 2003), 128 bits (Millberg et al. 2004), and 256
bits (Chi and Chen 2004)], Salminen et al. (2008) recommended the usage of
32-bit flit size and the same link width for mesh topology. Tilera’s 64-core-based
TILE64 processor chip, implemented in 90-nm technology, uses 32-bit-wide
two unidirectional inter-router links where the routers are connected in an
8 × 8 two-dimensional (2D) mesh fashion (Wentzlaff et al. 2007). Intel’s 80-corebased Teraflops research chip (Vangal et al. 2008) also uses 32-bit flit size and
39-bit wider links (including some handshaking signals) in 65-nm technology
where the routers are connected in an 8 × 10 mesh network. XPIPES (Bertozzi
and Benini 2004) and Dy-AD mesh (Hu and Marculescu 2004) also use 32-bit
link width in 100- and 160-nm technologies, respectively. Considering all these
examples, this chapter also uses both flit size and link width equal to 32 bits for
all the networks under consideration, keeping the wire dimension unchanged.
4.4 Simulation Results and Analysis of MoT Network
with WH Router
In this section, the evaluation methodology mentioned is applied to find out
the performance and energy consumption of MoT-based network consisting
of 32 IP cores by varying the offered load and locality factor in a self-similar
traffic. In the WH router architecture, FIFOs of depth 6 are used at both input
and output channels.