9
Introduction to Compact Models
In the meanwhile, BSIM has been continuously updated and extended to
accurately model the physical effects observed in sub-100 nm regime. In 2000,
BSIM4, version BSIM4.1.0, was released [55]. BSIM4 offers several improvements over BSIM3, including the traditional I–V modeling of intrinsic transistor, the transistor’s noise modeling, and the incorporation of extrinsic
parasitics. Some of the salient features of BSIM4 are an accurate model of the
intrinsic input resistance for RF, high-frequency analog and high-speed digital
applications, flexible substrate resistance network for RF modeling, an accurate channel thermal noise model along with a noise partition model for the
induced gate noise, an NQS model consistent with the gate resistance-based
RF model, an accurate gate direct tunneling model, a geometry- dependent
parasitics model for various source-drain connections and multifinger devices,
improved model for steep vertical retrograde doping profiles, better model for
halo-implanted devices in V th , bulk charge effect model, and output resistance,
asymmetrical and bias-dependent source-drain resistance, QM charge-layer
model for both I–V and C–V, gate-induced drain/source leakage (GIDL/GISL)
current model, and improved unified 1/f noise model [55–57].
1.2.2.2 Surface Potential–Based Compact MOSFET Modeling
In the surface potential–based modeling approach [23,37], f s is solved at the
two ends of the MOS channel. The terminal charges, currents, and derivatives
are then calculated from f s . During 1980s, a considerable progress has been
made to solve f s efficiently from the implicit f s equation. In 1985, Bagheri and
Tsividis reported an efficient algorithm [58] to solve these implicit f s equations
using Schroder series method [59,60], which is based on Taylor series expansion of the inverse function, provided a good initial guess such as the zeroorder relationship [61] is used. It is reported that at most only two iterations are
required to achieve an excellent estimation of f s0 or f sL in all operating regions.
In 1994, Arora et al. reported an efficient f s -based MOSFET model referred
to as the “PCIM” for in-house circuit simulation of Digital Equipment
Corporation’s (DEC) Alpha chip [62]. Based on the source-side-only surface
potential proposed by Park [63], Rios et al. in 1995 reported a model that is
shown to be practical and efficient and used it in DEC’s Alpha chip design
from 1996, featuring automatic and physical transitions between partially
and fully depleted modes of Silicon-on-Insulator (SOI) operations [64,65]. The
source-side-only solution was used to offer a good compromise between the
accuracy and simplicity, and the solution speed required for practical applications. This approach was shown to avoid solving for f s on the drain side,
while providing a simple and self-consistent treatment of carrier velocity
saturation. In addition, the appropriate treatment of the body charge linearization and the effective drain bias was used to maintain source-drain symmetry. The solution method preserves source-drain symmetry and produces
the correct drain current behavior near drain voltage, V ds = 0. It was reported
that in the source-side-only approach, simple, explicit, and self-consistent V dsat
Introduction to Compact Models
In the meanwhile, BSIM has been continuously updated and extended to
accurately model the physical effects observed in sub-100 nm regime. In 2000,
BSIM4, version BSIM4.1.0, was released [55]. BSIM4 offers several improvements over BSIM3, including the traditional I–V modeling of intrinsic transistor, the transistor’s noise modeling, and the incorporation of extrinsic
parasitics. Some of the salient features of BSIM4 are an accurate model of the
intrinsic input resistance for RF, high-frequency analog and high-speed digital
applications, flexible substrate resistance network for RF modeling, an accurate channel thermal noise model along with a noise partition model for the
induced gate noise, an NQS model consistent with the gate resistance-based
RF model, an accurate gate direct tunneling model, a geometry- dependent
parasitics model for various source-drain connections and multifinger devices,
improved model for steep vertical retrograde doping profiles, better model for
halo-implanted devices in V th , bulk charge effect model, and output resistance,
asymmetrical and bias-dependent source-drain resistance, QM charge-layer
model for both I–V and C–V, gate-induced drain/source leakage (GIDL/GISL)
current model, and improved unified 1/f noise model [55–57].
1.2.2.2 Surface Potential–Based Compact MOSFET Modeling
In the surface potential–based modeling approach [23,37], f s is solved at the
two ends of the MOS channel. The terminal charges, currents, and derivatives
are then calculated from f s . During 1980s, a considerable progress has been
made to solve f s efficiently from the implicit f s equation. In 1985, Bagheri and
Tsividis reported an efficient algorithm [58] to solve these implicit f s equations
using Schroder series method [59,60], which is based on Taylor series expansion of the inverse function, provided a good initial guess such as the zeroorder relationship [61] is used. It is reported that at most only two iterations are
required to achieve an excellent estimation of f s0 or f sL in all operating regions.
In 1994, Arora et al. reported an efficient f s -based MOSFET model referred
to as the “PCIM” for in-house circuit simulation of Digital Equipment
Corporation’s (DEC) Alpha chip [62]. Based on the source-side-only surface
potential proposed by Park [63], Rios et al. in 1995 reported a model that is
shown to be practical and efficient and used it in DEC’s Alpha chip design
from 1996, featuring automatic and physical transitions between partially
and fully depleted modes of Silicon-on-Insulator (SOI) operations [64,65]. The
source-side-only solution was used to offer a good compromise between the
accuracy and simplicity, and the solution speed required for practical applications. This approach was shown to avoid solving for f s on the drain side,
while providing a simple and self-consistent treatment of carrier velocity
saturation. In addition, the appropriate treatment of the body charge linearization and the effective drain bias was used to maintain source-drain symmetry. The solution method preserves source-drain symmetry and produces
the correct drain current behavior near drain voltage, V ds = 0. It was reported
that in the source-side-only approach, simple, explicit, and self-consistent V dsat