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MOSFET Capacitance Models
extrinsic or parasitic capacitances. First of all, the widely used simple Meyer
intrinsic capacitance model is presented. We have derived the expressions
for the terminal charges and capacitances and discussed the merits and
demerits of the Meyer model. In order to overcome the limitations of Meyer
model, more accurate charge-based capacitance model for both the long and
short channel devices are presented. The validity and limitations of quasistatic assumptions in capacitance modeling are also discussed. Finally, the
extrinsic capacitances such as the MOSFET S/D overlap capacitance and S/D
junction capacitances are presented.
Exercises
6.1 Complete the mathematical steps to show that the linear region
capacitances of MOSFETs are given by Equation 6.20.
6.2 Plot the normalized capacitance C/C oxt versus (V gs − V th ) characteristics for each of the components of gate capacitance C GB , C GS , and C GD
for an nMOSFET device with W = 1 μm, L = 250 nm, and T ox = 10 nm;
consider the biasing condition −2.0 V < V gs < 3.0 V and V ds = 1, 2, and
3 V. Clearly state any assumptions you make and explain your plots.
6.3 Show that the channel charge partition for a MOSFET device with
channel length L and channel width W at the drain end is given by
Equation 6.45.
MOSFET Capacitance Models
extrinsic or parasitic capacitances. First of all, the widely used simple Meyer
intrinsic capacitance model is presented. We have derived the expressions
for the terminal charges and capacitances and discussed the merits and
demerits of the Meyer model. In order to overcome the limitations of Meyer
model, more accurate charge-based capacitance model for both the long and
short channel devices are presented. The validity and limitations of quasistatic assumptions in capacitance modeling are also discussed. Finally, the
extrinsic capacitances such as the MOSFET S/D overlap capacitance and S/D
junction capacitances are presented.
Exercises
6.1 Complete the mathematical steps to show that the linear region
capacitances of MOSFETs are given by Equation 6.20.
6.2 Plot the normalized capacitance C/C oxt versus (V gs − V th ) characteristics for each of the components of gate capacitance C GB , C GS , and C GD
for an nMOSFET device with W = 1 μm, L = 250 nm, and T ox = 10 nm;
consider the biasing condition −2.0 V < V gs < 3.0 V and V ds = 1, 2, and
3 V. Clearly state any assumptions you make and explain your plots.
6.3 Show that the channel charge partition for a MOSFET device with
channel length L and channel width W at the drain end is given by
Equation 6.45.