Microprocessors
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13.14.1 Programmable Timer/Counter
The programmable timer/counter is used for the generation of an accurate time delay for event counting,
rate generation, complex waveform generation applications and so on. Examples of programmable
timer/counter devices include Intel’s 8254 and 8253 family of devices. Intel 8254 contains three 16-bit
counters that can be programmed to operate in several different modes. Some of the functions common
to microcomputers and implementable with 8254 are a real-time clock, an event counter, a digital
one-shot, programmable rate generator, a square-wave generator, a binary rate multiplier, a complex
waveform generator and a complex motor controller. It is available in 24-pin CERDIP and plastic DIP
packages.
13.14.2 Programmable Peripheral Interface
Programmable peripheral interface (PPI) devices are used to interface the peripheral devices with
the microprocessors. 8255 PPI is a widely used programmable parallel I/O device. It is available in
PDIP, CerDIP, PLCC and MQPF packages. 8255 can be programmed to transfer data under various
conditions, from simple I/O to interrupt I/O. It can function in bit reset (BSR) mode or I/O mode. In
I/O mode it has three ports, namely port A, port B and port C. The I/O mode is further divided into
three different modes, namely mode 0, mode 1 and mode 2. In mode 0, all ports function as simple
I/O ports. Mode 1 is a handshake mode whereby port A and/or B use bits from port C as handshake
signals. In mode 2, port A can be set up for bidirectional data transfer using handshake signals from
port C, and port B can be set up either in mode 0 or in mode 1. In BSR mode, individual bits in port
C can be set or reset.
13.14.3 Programmable Interrupt Controller
A programmable interrupt controller (PIC) is a device that allows priority levels to be assigned to its
interrupt outputs. It functions as an overall manager in an interrupt-driven system environment. When
the device has multiple interrupt outputs, it will assert them in the order of their relative priority.
Common modes of a PIC include hard priorities, rotating priorities and cascading priorities. Intel 8259
is a family of programmable interrupt controllers (PICs) designed and developed for use with the Intel
8085 and Intel 8086 microprocessors. The family originally consisted of the 8259, 8259A, and 8259B
PICs, although a number of manufacturers make a wide range of compatible chips today.
It handles up to eight vectored priority interrupts for the CPU. It is designed to minimize the software
and real-time overhead in handling multi-level priority interrupts. It accepts requests from peripheral
equipment, determines which of the incoming requests is of the highest priority, ascertains whether
an incoming request has a higher priority value than the level currently being serviced and issues an
interrupt to the CPU on the basis of this determination.
13.14.4 DMA Controller
In a direct memory access (DMA) data transfer scheme, data are transferred directly from an I/O device
to memory, or vice versa, without going through the CPU. The DMA controller is used to control the
process of data transfer. Its primary function is to generate, upon a peripheral request, a sequential
memory address that will allow the peripheral to read or write data directly to or from memory. One of
the popular known programmable DMA controllers is Intel’s 8257. It is a four-channel direct memory
access (DMA) controller. It is specifically designed to simplify the transfer of data at high speeds
561
13.14.1 Programmable Timer/Counter
The programmable timer/counter is used for the generation of an accurate time delay for event counting,
rate generation, complex waveform generation applications and so on. Examples of programmable
timer/counter devices include Intel’s 8254 and 8253 family of devices. Intel 8254 contains three 16-bit
counters that can be programmed to operate in several different modes. Some of the functions common
to microcomputers and implementable with 8254 are a real-time clock, an event counter, a digital
one-shot, programmable rate generator, a square-wave generator, a binary rate multiplier, a complex
waveform generator and a complex motor controller. It is available in 24-pin CERDIP and plastic DIP
packages.
13.14.2 Programmable Peripheral Interface
Programmable peripheral interface (PPI) devices are used to interface the peripheral devices with
the microprocessors. 8255 PPI is a widely used programmable parallel I/O device. It is available in
PDIP, CerDIP, PLCC and MQPF packages. 8255 can be programmed to transfer data under various
conditions, from simple I/O to interrupt I/O. It can function in bit reset (BSR) mode or I/O mode. In
I/O mode it has three ports, namely port A, port B and port C. The I/O mode is further divided into
three different modes, namely mode 0, mode 1 and mode 2. In mode 0, all ports function as simple
I/O ports. Mode 1 is a handshake mode whereby port A and/or B use bits from port C as handshake
signals. In mode 2, port A can be set up for bidirectional data transfer using handshake signals from
port C, and port B can be set up either in mode 0 or in mode 1. In BSR mode, individual bits in port
C can be set or reset.
13.14.3 Programmable Interrupt Controller
A programmable interrupt controller (PIC) is a device that allows priority levels to be assigned to its
interrupt outputs. It functions as an overall manager in an interrupt-driven system environment. When
the device has multiple interrupt outputs, it will assert them in the order of their relative priority.
Common modes of a PIC include hard priorities, rotating priorities and cascading priorities. Intel 8259
is a family of programmable interrupt controllers (PICs) designed and developed for use with the Intel
8085 and Intel 8086 microprocessors. The family originally consisted of the 8259, 8259A, and 8259B
PICs, although a number of manufacturers make a wide range of compatible chips today.
It handles up to eight vectored priority interrupts for the CPU. It is designed to minimize the software
and real-time overhead in handling multi-level priority interrupts. It accepts requests from peripheral
equipment, determines which of the incoming requests is of the highest priority, ascertains whether
an incoming request has a higher priority value than the level currently being serviced and issues an
interrupt to the CPU on the basis of this determination.
13.14.4 DMA Controller
In a direct memory access (DMA) data transfer scheme, data are transferred directly from an I/O device
to memory, or vice versa, without going through the CPU. The DMA controller is used to control the
process of data transfer. Its primary function is to generate, upon a peripheral request, a sequential
memory address that will allow the peripheral to read or write data directly to or from memory. One of
the popular known programmable DMA controllers is Intel’s 8257. It is a four-channel direct memory
access (DMA) controller. It is specifically designed to simplify the transfer of data at high speeds