Flip-Flops and Related Devices
407
waveform A is in a logic ‘1’ state. Thus, the Q output in this case will always be in a logic ‘1’
state.
(b) By interchanging the connections of waveforms A and B as shown in Fig. 10.53(b), the Q output
will be in a logic ‘0’ state as long as waveform A leads waveform B in phase. In this case, on
every occurrence of the leading edge of waveform A (clock input), waveform B (D input) is in a
logic ‘0’ state.
10.11 Application-Relevant Data
Table 10.1 lists popular type numbers of flip-flops belonging to TTL, CMOS and ECL logic families.
Application-relevant information of some of the popular type numbers is given in the companion
website. The information given includes the pin connection diagram, package style and function table.
Table 10.1 Popular type numbers of flip-flops belonging to the TTL, CMOS and ECL logic families.
IC type
Function
Logic
number
family
54/7473
Dual J -K negative edge-triggered flip-flop with CLEAR
TTL
54/7474
Dual D-type positive edge-triggered flip-flop with PRESET and CLEAR
TTL
54/7475
Four-bit D-type latch
TTL
54/7476
Dual J -K flip-flop with PRESET and CLEAR
TTL
54/7478
Dual J -K flip-flop with PRESET and CLEAR
TTL
54/74107
Dual J -K flip-flop with CLEAR
TTL
54/74109
Dual J -K positive edge-triggered flip-flop with PRESET and CLEAR
TTL
54/74112
Dual J -K negative edge-triggered flip-flop with PRESET and CLEAR
TTL
54/74113
Dual J -K negative edge-triggered flip-flop with PRESET
TTL
54/74114
Dual J -K negative edge-triggered flip-flop with PRESET and CLEAR
TTL
54/74121
Monostable multivibrator
TTL
54/74122
Retriggerable monostable multivibrator
TTL
54/74123
Dual retriggerable monostable multivibrator
TTL
54/74174
Hex D-type flip-flop with CLEAR
TTL
54/74175
Quad edge triggered D-type flip-flop with CLEAR
TTL
54/74221
Dual monostable multivibrator
TTL
54/74256
Dual four-bit addressable latch
TTL
54/74259
Eight-bit addressable latch
TTL
54/74273
Octal D-type flip-flop with MASTER RESET
TTL
54/74279
Quad SET/RESET latch
TTL
54/74373
Octal transparent latch (three-state)
TTL
54/74374
Octal D-type flip-flop (three-state)
TTL
54/74377
Octal D-type flip-flop with common ENABLE
TTL
54/74378
Hex D-type flip-flop with ENABLE
TTL
54/74379
Four-bit D-type flip-flop with ENABLE
TTL
54/74533
Octal transparent latch (three-state)
TTL
54/74534
Octal D-type flip-flop (three-state)
TTL
54/74573
Octal D-type latch (three-state)
TTL
54/74574
Octal D-type flip-flop (three-state)
TTL
(continued overleaf)
407
waveform A is in a logic ‘1’ state. Thus, the Q output in this case will always be in a logic ‘1’
state.
(b) By interchanging the connections of waveforms A and B as shown in Fig. 10.53(b), the Q output
will be in a logic ‘0’ state as long as waveform A leads waveform B in phase. In this case, on
every occurrence of the leading edge of waveform A (clock input), waveform B (D input) is in a
logic ‘0’ state.
10.11 Application-Relevant Data
Table 10.1 lists popular type numbers of flip-flops belonging to TTL, CMOS and ECL logic families.
Application-relevant information of some of the popular type numbers is given in the companion
website. The information given includes the pin connection diagram, package style and function table.
Table 10.1 Popular type numbers of flip-flops belonging to the TTL, CMOS and ECL logic families.
IC type
Function
Logic
number
family
54/7473
Dual J -K negative edge-triggered flip-flop with CLEAR
TTL
54/7474
Dual D-type positive edge-triggered flip-flop with PRESET and CLEAR
TTL
54/7475
Four-bit D-type latch
TTL
54/7476
Dual J -K flip-flop with PRESET and CLEAR
TTL
54/7478
Dual J -K flip-flop with PRESET and CLEAR
TTL
54/74107
Dual J -K flip-flop with CLEAR
TTL
54/74109
Dual J -K positive edge-triggered flip-flop with PRESET and CLEAR
TTL
54/74112
Dual J -K negative edge-triggered flip-flop with PRESET and CLEAR
TTL
54/74113
Dual J -K negative edge-triggered flip-flop with PRESET
TTL
54/74114
Dual J -K negative edge-triggered flip-flop with PRESET and CLEAR
TTL
54/74121
Monostable multivibrator
TTL
54/74122
Retriggerable monostable multivibrator
TTL
54/74123
Dual retriggerable monostable multivibrator
TTL
54/74174
Hex D-type flip-flop with CLEAR
TTL
54/74175
Quad edge triggered D-type flip-flop with CLEAR
TTL
54/74221
Dual monostable multivibrator
TTL
54/74256
Dual four-bit addressable latch
TTL
54/74259
Eight-bit addressable latch
TTL
54/74273
Octal D-type flip-flop with MASTER RESET
TTL
54/74279
Quad SET/RESET latch
TTL
54/74373
Octal transparent latch (three-state)
TTL
54/74374
Octal D-type flip-flop (three-state)
TTL
54/74377
Octal D-type flip-flop with common ENABLE
TTL
54/74378
Hex D-type flip-flop with ENABLE
TTL
54/74379
Four-bit D-type flip-flop with ENABLE
TTL
54/74533
Octal transparent latch (three-state)
TTL
54/74534
Octal D-type flip-flop (three-state)
TTL
54/74573
Octal D-type latch (three-state)
TTL
54/74574
Octal D-type flip-flop (three-state)
TTL
(continued overleaf)
