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Digital Electronics
2
10
9
8
7
6
5
4
CLK
3
11
12
13
14
15
16
17
20
18
19
1
I 0
I 1
I 2
I 3
I 4
I 5
I 6
I 7
GND
V cc
Q 7
Q 6
Q 5
Q 4
Q 3
Q 2
Q 1
Q 0
OE
AND
OR
Array
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
(b)
Figure 9.35 (continued).
GAL 22V10 uses E
2 CMOS (electrically erasable CMOS) technology which allows the device to
be reprogrammable through the use of an electrically erasable (E
2 floating-gate technology and
consume much less power compared with bipolar 22V10 devices owing to the use of advanced CMOS
technology. The device specifies 100 erase/write cycles, a 50–75 % saving in power consumption
compared with bipolar equivalents and a maximum propagation delay of 4 ns. Each of the output
logic macrocells offers two primary functional modes, which include combinational I/O and registered
modes. The type of mode (whether combinational I/O or registered) and the output polarity (whether
active HIGH or active LOW) are decided by the selection inputs S 0 and S 1 , which are normally
controlled by the logic compiler. For S 1 S 0 equal to 00, 01, 10 and 11, outputs are active LOW registered,
active LOW combinational, active HIGH registered and active HIGH combinational respectively.