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Digital Electronics
D
C
B
A
Programmable AND-array
Y1
Y2
Programmable OR-array
Figure 9.4 Internal architecture of a PLA device.
is usually much less than 2
m , and the number of inputs of each of the OR gates equals the number of
AND gates. Each OR gate can generate an arbitrary Boolean function with a maximum of minterms
equal to the number of AND gates. Figure 9.4 shows the internal architecture of a PLA device with
four input lines, a programmable array of eight AND gates at the input and a programmable array of
two OR gates at the output. A PLA device makes more efficient use of logic capacity than a PROM.
However, it has its own disadvantages resulting from two sets of programmable fuses, which makes it
relatively more difficult to manufacture, program and test.
9.2.3 Programmable Array Logic
Programmable array logic (PAL) architecture has a programmable AND array at the input and a fixed
OR array at the output. The programmable AND array of a PAL device is similar to that of a PLA
device. That is, the number of programmable AND gates is usually smaller than the number required