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Digital Electronics
3. In the case of programmable logic devices, users can change the circuit as often as they want to
until the design operates to their satisfaction. PLDs offer to the users much more flexibility during
the design cycle. Design iterations are nothing but changes to the programming file.
4. Fixed logic devices have an edge for large-volume applications as they can be mass produced
more economically. They are also the preferred choice in applications requiring the highest
performance level.
9.2 Programmable Logic Devices – An Overview
There are many types of programmable logic device, distinguishable from one another in terms of
architecture, logic capacity, programmability and certain other specific features. In this section, we
will briefly discuss commonly used PLDs and their salient features. A detailed description of each of
them will follow in subsequent sections.
9.2.1 Programmable ROMs
PROM (Programmable Read Only Memory) and EPROM (Erasable Programmable Read Only
Memory) can be considered to be predecessors to PLDs. The architecture of a programmable ROM
allows the user to hardware-implement an arbitrary combinational function of a given number of inputs.
When used as a memory device, n inputs of the ROM (called address lines in this case) and m outputs
(called data lines) can be used to store 2
n m-bit words. When used as a PLD, it can be used to implement
m different combinational functions, with each function being a chosen function of n variables. Any
conceivable n-variable Boolean function can be made to appear at any of the m output lines. A
generalized ROM device with n inputs and m outputs has 2
n hard-wired AND gates at the input and m
programmable OR gates at the output. Each AND gate has n inputs, and each OR gate has 2
n inputs.
Thus, each OR gate can be used to generate any conceivable Boolean function of n variables, and this
generalized ROM can be used to produce m arbitrary n-variable Boolean functions. The AND array
produces all possible minterms of a given number of input variables, and the programmable OR array
allows only the desired minterms to appear at their inputs. Figure 9.3 shows the internal architecture
of a PROM having four input lines, a hard-wired array of 16 AND gates and a programmable array
of four OR gates. A cross (×) indicates an intact (or unprogrammed) fusible link or interconnection,
and a dot (•) indicates a hard-wired interconnection. PROMs, EPROMs and EEPROMs (Electrically
Erasable Programmable Read Only Memory) can be programmed using standard PROM programmers.
One of the major disadvantages of PROMs is their inefficient use of logic capacity. It is not economical
to use PROMs for all those applications where only a few minterms are needed. Other disadvantages
include relatively higher power consumption and an inability to provide safe covers for asynchronous
logic transitions. They are usually much slower than the dedicated logic circuits. Also, they cannot be
used to implement sequential logic owing to the absence of flip-flops.
9.2.2 Programmable Logic Array
A programmable logic array (PLA) device has a programmable AND array at the input and a
programmable OR array at the output, which makes it one of the most versatile PLDs. Its architecture
differs from that of a PROM in the following respects. It has a programmable AND array rather than
a hard-wired AND array. The number of AND gates in an m-input PROM is always equal to 2
m . In
the case of a PLA, the number of AND gates in the programmable AND array for m input variables
Digital Electronics
3. In the case of programmable logic devices, users can change the circuit as often as they want to
until the design operates to their satisfaction. PLDs offer to the users much more flexibility during
the design cycle. Design iterations are nothing but changes to the programming file.
4. Fixed logic devices have an edge for large-volume applications as they can be mass produced
more economically. They are also the preferred choice in applications requiring the highest
performance level.
9.2 Programmable Logic Devices – An Overview
There are many types of programmable logic device, distinguishable from one another in terms of
architecture, logic capacity, programmability and certain other specific features. In this section, we
will briefly discuss commonly used PLDs and their salient features. A detailed description of each of
them will follow in subsequent sections.
9.2.1 Programmable ROMs
PROM (Programmable Read Only Memory) and EPROM (Erasable Programmable Read Only
Memory) can be considered to be predecessors to PLDs. The architecture of a programmable ROM
allows the user to hardware-implement an arbitrary combinational function of a given number of inputs.
When used as a memory device, n inputs of the ROM (called address lines in this case) and m outputs
(called data lines) can be used to store 2
n m-bit words. When used as a PLD, it can be used to implement
m different combinational functions, with each function being a chosen function of n variables. Any
conceivable n-variable Boolean function can be made to appear at any of the m output lines. A
generalized ROM device with n inputs and m outputs has 2
n hard-wired AND gates at the input and m
programmable OR gates at the output. Each AND gate has n inputs, and each OR gate has 2
n inputs.
Thus, each OR gate can be used to generate any conceivable Boolean function of n variables, and this
generalized ROM can be used to produce m arbitrary n-variable Boolean functions. The AND array
produces all possible minterms of a given number of input variables, and the programmable OR array
allows only the desired minterms to appear at their inputs. Figure 9.3 shows the internal architecture
of a PROM having four input lines, a hard-wired array of 16 AND gates and a programmable array
of four OR gates. A cross (×) indicates an intact (or unprogrammed) fusible link or interconnection,
and a dot (•) indicates a hard-wired interconnection. PROMs, EPROMs and EEPROMs (Electrically
Erasable Programmable Read Only Memory) can be programmed using standard PROM programmers.
One of the major disadvantages of PROMs is their inefficient use of logic capacity. It is not economical
to use PROMs for all those applications where only a few minterms are needed. Other disadvantages
include relatively higher power consumption and an inability to provide safe covers for asynchronous
logic transitions. They are usually much slower than the dedicated logic circuits. Also, they cannot be
used to implement sequential logic owing to the absence of flip-flops.
9.2.2 Programmable Logic Array
A programmable logic array (PLA) device has a programmable AND array at the input and a
programmable OR array at the output, which makes it one of the most versatile PLDs. Its architecture
differs from that of a PROM in the following respects. It has a programmable AND array rather than
a hard-wired AND array. The number of AND gates in an m-input PROM is always equal to 2
m . In
the case of a PLA, the number of AND gates in the programmable AND array for m input variables