294
Digital Electronics
Table 8.12 (continued).
IC Type Function
Logic
number
family
4515
1-of-16 decoder/demultiplexer with input latch
CMOS
4532
Eight-line to three-line priority encoder
CMOS
4539
Dual four-input multiplexer
CMOS
4543
BCD to seven-segment latch/decoder/driver for LCD
displays
CMOS
4555
Dual 1-of-4 decoder/demultiplexers
CMOS
4556
Dual 1-of-4 decoder/demultiplexers
CMOS
4723
Dual four-bit addressable latch
CMOS
4724
Eight-bit addressable latch
CMOS
10132
Dual two-input multiplexer with latch and common
reset
ECL
10134
Dual multiplexer with latch
ECL
10158
Quad two-input multiplexer (non-inverting)
ECL
10159
Quad two-input multiplexer (inverting)
ECL
10161
3-to-8 line decoder (LOW)
ECL
10162
3-to-8 line decoder (HIGH)
ECL
10164
Eight-line multiplexer
ECL
10165
Eight-input priority encoder
ECL
10171
Dual 2-to-4 line decoder (LOW)
ECL
10172
Dual 2-to-4 line decoder (HIGH)
ECL
10173
Quad two-input multiplexer/latch
ECL
10174
Dual 4-to-1 multiplexer
ECL
Review Questions
1. What is a multiplexer circuit? Briefly describe one or two applications of a multiplexer?
2. Is it possible to enhance the capability of an available multiplexer in terms of the number of input
lines it can handle by using more than one device? If yes, briefly describe the procedure to do so,
with the help of an example.
3. What is an encoder? How does a priority encoder differ from a conventional encoder? With the
help of a truth table, briefly describe the functioning of a 10-line to four-line priority encoder with
active LOW inputs and outputs and priority assigned to the higher-order inputs.
4. What is a demultiplexer and how does it differ from a decoder? Can a decoder be used as a
demultiplexer? If yes, from where do we get the required input line?
5. Briefly describe how we can use a decoder optimally to implement a given Boolean function?
Illustrate your answer with the help of an example.
6. Draw truth tables for the following:
(a) an 8-to-1 multiplexer with active LOW inputs and an active LOW ENABLE input;
(b) a four-line to 16-line decoder with active HIGH inputs and active LOW outputs and an active
LOW ENABLE input;
(c) an eight-line to three-line priority encoder with active LOW inputs and outputs and an active
LOW ENABLE input.