Logic Families
185
Review Questions
1. What do you understand by the term logic family? What is the significance of the logic family
with reference to digital integrated circuits (ICs)?
2. Briefly describe propagation delay, power dissipation, speed–power product, fan-out and noise
margin parameters, with particular reference to their significance as regards the suitability of the
logic family for a given application.
3. Compare the standard TTL, low-power Schottky TTL and Schottky TTL on the basis of speed,
power dissipation and fan-out capability.
4. What is the totem-pole output stage? What are its advantages?
5. What are the basic differences between buffered and unbuffered CMOS devices? How is a buffered
NAND usually implemented in 4000B-series CMOS logic?
6. With the help of relevant circuit schematics, briefly describe the operation of CMOS NAND and
NOR gates.
7. Compare standard TTL and 4000B CMOS families on the basis of speed and power dissipation
parameters.
8. Why is ECL called nonsaturating logic? What is the main advantage accruing from this? With the
help of a relevant circuit schematic, briefly describe the operation of ECL OR/NOR logic.
9. What is the main criterion for the suitability of a logic family for use in fabricating LSI and VLSI
logic functions? Name any two popular candidates and compare their features.
10. Why is it not recommended to leave unused logic inputs floating? What should we do to such
inputs in the case of TTL and CMOS logic gates?
11. What special precautions should we observe in handling and using CMOS ICs?
12. With the help of suitable schematics, briefly describe how you would achieve TTL-to-CMOS and
CMOS-to-TTL interfaces?
13. What is Bi-CMOS logic? What are its advantages?
14. What in a logic family decides the fan-out, speed of operation, noise immunity and power
dissipation?
Problems
1. The data sheet of a quad two-input AND gate (type 74S08) specifies the propagation delay and
power supply parameters as V CC = 5.0 V (typical), I CCH (for all four gates) = 18 mA, I CCL (for all four
gates) = 32 mA, t pLH = 4.5 ns and t pHL = 5.0 ns. Determine the speed–power product specification.
148.4 pJ
2. How many inputs of a low-power Schottky TTL NAND can be reliably driven from a single output
of a Schottky TTL NAND, given the following relevant specifications for the devices of two TTL
subfamilies:
Schottky TTL: I OH = 1.0 mA; I IH = 0.05 mA; I OL = 20.0 mA; I IL = 2.0 mA
Low-power Schottky TTL: I OH = 0.4 mA; I IH = 0.02 mA; I OL = 8.0 mA; I IL = 0.4 mA
50
3. Refer to the logic diagram in Fig. 5.66. Determine the current being sourced by the NAND gate
when its output is HIGH and also the current sunk by it when its output is LOW, given that
I IH (AND gate) = 0.02 mA, I IL (AND gate) = 0.4 mA, I IH (OR gate) = 0.04 mA, I IL (OR gate) =
1.6 mA, I OH (NAND gate) = 1.0 mA, I OL (NAND gate) = 20.0 mA.
HIGH-state current = 0.08 mA; LOW-state current = 2.0 mA
185
Review Questions
1. What do you understand by the term logic family? What is the significance of the logic family
with reference to digital integrated circuits (ICs)?
2. Briefly describe propagation delay, power dissipation, speed–power product, fan-out and noise
margin parameters, with particular reference to their significance as regards the suitability of the
logic family for a given application.
3. Compare the standard TTL, low-power Schottky TTL and Schottky TTL on the basis of speed,
power dissipation and fan-out capability.
4. What is the totem-pole output stage? What are its advantages?
5. What are the basic differences between buffered and unbuffered CMOS devices? How is a buffered
NAND usually implemented in 4000B-series CMOS logic?
6. With the help of relevant circuit schematics, briefly describe the operation of CMOS NAND and
NOR gates.
7. Compare standard TTL and 4000B CMOS families on the basis of speed and power dissipation
parameters.
8. Why is ECL called nonsaturating logic? What is the main advantage accruing from this? With the
help of a relevant circuit schematic, briefly describe the operation of ECL OR/NOR logic.
9. What is the main criterion for the suitability of a logic family for use in fabricating LSI and VLSI
logic functions? Name any two popular candidates and compare their features.
10. Why is it not recommended to leave unused logic inputs floating? What should we do to such
inputs in the case of TTL and CMOS logic gates?
11. What special precautions should we observe in handling and using CMOS ICs?
12. With the help of suitable schematics, briefly describe how you would achieve TTL-to-CMOS and
CMOS-to-TTL interfaces?
13. What is Bi-CMOS logic? What are its advantages?
14. What in a logic family decides the fan-out, speed of operation, noise immunity and power
dissipation?
Problems
1. The data sheet of a quad two-input AND gate (type 74S08) specifies the propagation delay and
power supply parameters as V CC = 5.0 V (typical), I CCH (for all four gates) = 18 mA, I CCL (for all four
gates) = 32 mA, t pLH = 4.5 ns and t pHL = 5.0 ns. Determine the speed–power product specification.
148.4 pJ
2. How many inputs of a low-power Schottky TTL NAND can be reliably driven from a single output
of a Schottky TTL NAND, given the following relevant specifications for the devices of two TTL
subfamilies:
Schottky TTL: I OH = 1.0 mA; I IH = 0.05 mA; I OL = 20.0 mA; I IL = 2.0 mA
Low-power Schottky TTL: I OH = 0.4 mA; I IH = 0.02 mA; I OL = 8.0 mA; I IL = 0.4 mA
50
3. Refer to the logic diagram in Fig. 5.66. Determine the current being sourced by the NAND gate
when its output is HIGH and also the current sunk by it when its output is LOW, given that
I IH (AND gate) = 0.02 mA, I IL (AND gate) = 0.4 mA, I IH (OR gate) = 0.04 mA, I IL (OR gate) =
1.6 mA, I OH (NAND gate) = 1.0 mA, I OL (NAND gate) = 20.0 mA.
HIGH-state current = 0.08 mA; LOW-state current = 2.0 mA